SH7727 Datasheet, PDF (453/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.1.2 Block Diagram
Figure 14.1 is a block diagram of the DMAC.
X/Y memory
On-chip
supporting
module
USBF
SIOF
Selector Ch0 to Ch3
CHRAR
DREQ0
SCIF
A/D converter
CMT
DEIn
DACK0, DRAK0
DMAC module
Interation
control
SARn
Register
control
Start-up
control
DARn
DMATCRn
CHCRn
Request
priority
control
DMAOR
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
Bus interface
Bus state
controller
Legend:
DMAOR: DMAC operation register
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
CHRAR: DMA channel assign register
DEIn:
DMA transfer-end interrupt request to
CPU
n:
0 to 3
Figure 14.1 DMAC Block Diagram
Rev. 5.00 Dec 12, 2005 page 381 of 1034
REJ09B0254-0500