SH7727 Datasheet, PDF (454/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.1.3 Pin Configuration
Table 14.1 shows the DMAC pins.
Table 14.1 Pin Configuration
Channel Name
Symbol I/O
0
DMA transfer request DREQ0 Input
DREQ acknowledge DACK0 Output
DMA request
acknowledge
DRAK0 Output
Function
DMA transfer request input from
external device to channel 0
Strobe output to an external I/O at DMA
transfer request from external device to
channel 0
Output showing that DREQ0 has been
accepted
14.1.4 Register Configuration
Table 14.2 summarizes the DMAC registers. DMAC has a total of 18 registers, four registers for
each channel and two registers for controlling all channels.
Table 14.2 DMAC Registers
Channel
0
1
Name
Abbrevi-
ation
R/W
DMA source address
SAR0
R/W
register 0
DMA destination address DAR0
R/W
register 0
DMA transfer count
register 0
DMA channel control
register 0
DMATCR0 R/W
CHCR0 R/W^*1
DMA source address
SAR1
R/W
register 1
DMA destination address DAR1
R/W
register 1
DMA transfer count
register 1
DMA channel control
register 1
DMATCR1 R/W
CHCR1 R/W^*1
Initial
Value
Address
Register
Size
Undefined H'04000020
32 bits
(H'A4000020)^*4
Undefined H'04000024
32 bits
(H'A4000024)^*4
Undefined H'04000028
24 bits
(H'A4000028)^*4
H'00000000 H'0400002C 32 bits
(H'A400002C)^*4
Undefined H'04000030
32 bits
(H'A4000030)^*4
Undefined H'04000034
32 bits
(H'A4000034)^*4
Undefined H'04000038
24 bits
(H'A4000038)^*4
H'00000000 H'0400003C 32 bits
(H'A400003C)^*4
Access
Size
16, 32^*2
16, 32^*2
16, 32^*3
8, 16,
32^*2
16, 32^*2
16, 32^*2
16, 32^*3
8, 16,
32^*2
Rev. 5.00 Dec 12, 2005 page 382 of 1034
REJ09B0254-0500