SH7727 Datasheet, PDF (658/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.9 FIFO Control Register 2 (SCFCR2)
Bit:
Initial value:
R/W:
7
RTRG1
0
R/W
6
RTRG0
0
R/W
5
TTRG1
0
R/W
4
TTRG0
0
R/W
3
MCE
0
R/W
2
TFRST
0
R/W
1
RFRST
0
R/W
0
LOOP
0
R/W
The FIFO control register 2 (SCFCR2) resets the number of data in the transmit and receive FIFO
register 2, sets the number of trigger data, and contains the permit bit for the loop back test. The
SCFCR2 is always read and written by the CPU. It is initialized to H'00 by the reset, the module
standby function, or in the standby mode.
Bits 7 and 6—Trigger of the Number of Receive FIFO Data (RTRG1 and RTRG0): Set the
number of receive data which sets the receive data full (RDF) flag in the serial status register 2
(SCSSR2). These bits set the RDF flag when the number of receive data stored in the receive
FIFO register 2 (SCFRDR2) is increased more than the number of setting triggers listed below.
Bit 7: RTRG1
0
1
Bit 6: RTRG0
0
1
0
1
Number of Received Triggers
1
(Initial value)
4
8
14
Bits 5 and 4—Trigger of the Number of Transmit FIFO Data (TTRG1 and TTRG0): Set the
number of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag
in the serial status register 2 (SCSSR2). These bits set the TDFE flag when the number of
transmit data in the transmit FIFO data register 2 (SCFTDR2) is decreased less than the number of
setting triggers listed below.
Bit 5: TTRG1
Bit 4: TTRG0
Number of Transmitted Triggers
0
0
8 (8)*
1
4 (12)
1
0
2 (14)
1
1 (15)
Note: * Initial value. Values in brackets mean the number of empty SCFTDR2 when a flag occurs.
Rev. 5.00 Dec 12, 2005 page 586 of 1034
REJ09B0254-0500