SH7727 Datasheet, PDF (219/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 4 Exception Handling
4. PINT Pin Interrupts
Conditions: The PINT pin is asserted and SR.IMASK is lower than the PINT priority level and
the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding
to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR
are set to 1 and a branch occurs to VBR + H'0600. The received level is not set to SR.IMASK.
See section 7, Interrupt Controller (INTC), for more information.
5. On-Chip Peripheral Interrupts
Conditions: SR.IMASK is lower than the on-chip module (TMU, RTC, SCI, SIOF, SCIF, A/D,
DMAC, CPG, REF, PCC, USBH, USBF, LCDC, AFEIF) interrupt level and the BL bit in SR
is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding
to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR
are set to 1 and a branch occurs to VBR + H'0600. See section 7, Interrupt Controller (INTC),
for more information.
6. H-UDI Interrupt
Conditions: H-UDI interrupt command is input (see section 31.4.4, H-UDI Interrupt), the value
of the interrupt mask bits of SR is lower than 15, and the BL bit in SR is 0, the interrupt is
accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The SR
at the point the interrupt is accepted is saved to the SSR. H'5E0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR +
H'0600. See section 7, Interrupt Controller (INTC), for more information.
4.6 Usage Notes
• Return from exception handling
 Check the BL bit in SR with software. When the SPC and SSR have been saved to external
memory, set the BL bit in SR to 1 before restoring them.
 Issue an RTE instruction. Set the SPC in the PC and SSR in SR with the RTE instruction,
branch to the SPC address, and return from exception handling.
• Operation when exception or interrupt occurs while SR.BL = 1
 Interrupt: Acceptance is suppressed until the BL bit in SR is set to 0 by software. If there is
a request and the reception conditions are satisfied, the interrupt is accepted after the
Rev. 5.00 Dec 12, 2005 page 147 of 1034
REJ09B0254-0500