SH7727 Datasheet, PDF (510/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.5 Examples for Use
14.5.1 Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on)
In this example, DMA transfer is performed between the on-chip A/D converter (transfer source)
and the external memory (transfer destination) with the address reload function on. Table 14.8
shows the transfer conditions and register settings.
Table 14.8 Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory
Transfer Conditions
Transfer source: on-chip A/D converter
Transfer destination: external memory
Number of transfers: 128 (reloading 32 times)
Transfer source address: incremented
Transfer destination address: decremented
Transfer request source: A/D converter
Bus mode: burst
Transfer unit: long word
Interrupt request generated at end of transfer
Channel priority order: 0 > 2 > 3 > 1
Register
SAR2
DAR2
DMATCR2
CHCR2
Setting
H'04000080
H'00400000
H'00000080
H'00089E35
DMAOR
H'0101
When the address reload function is turned on, the value set in SAR returns to the initially set
value at each four transfers. In this example, when an interrupt request is generated from the AD
converter, longword data is read from the register in address H'04000080 of the A/D converter,
and the data is written to external memory address H'00400000. Since longword data has been
transferred, the values in SAR and DAR are H'04000084 and H'003FFFFC, respectively. The bus
right is retained and data transfers are successively performed because this transfer is in the burst
mode.
After four transfers end, fifth and sixth transfers are performed when the address reload function is
turned off, and the value in SAR is incremented by 4, such as H'0400008C, H'04000090,
H'04000094,.... When the address reload function is on, the DMA transfer stops after the fourth
transfer ends and the bus request signal to the CPU is cleared. At this time, the value stored in
SAR is not incremented from H'0400008C to H'04000090, but returns to the initially set value
H'04000080. The value in DAR continues being incremented regardless of the address reload
function setting.
Rev. 5.00 Dec 12, 2005 page 438 of 1034
REJ09B0254-0500