SH7727 Datasheet, PDF (449/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
13.2.5 USBH Li Bus Access
USB Host issues 1 to 4 burst request to LBSC as normal read or write action. Since the burst
length issued by USB Host is occasionally changed as FIFO pointer rises up or falls, it is not
supposed as 4 burst exactly.
BSC
SH7727
Synchronous
DRAM
(Area 3)
Bus arbitration
Bus
LBSC
Li bus
USBH
LCDC
Figure 13.1 Block Diagram of Li Bus Architecture
13.2.6 Setting of DMA Transfer with Bus Arbitration of Other Module
This LSI has five types of bus master: CPU, DMAC and Refresh (BSC system), and LCDC and
USBH (LBSC system). The following priority order is set for these buses.
1. The BSC and LBSC systems are the same in priority level.
2. In the BSC system, Refresh has the highest priority.
3. Between CPU and DMAC, DMAC is higher in priority when DMA burst setting is made. In
cycle steal, CPU and DMAC are the same in priority level.
4. LCDC and USBH are the same priority level in the LBSC system.
In cycle steal, the priority level of DMA transfer is very low. Therefore, if the DMAC transfer
speed may cause problems, it is recommended to use the level-input burst transfer setting for
DMAC, especially when DREQ signals from an external device can be negated.
Rev. 5.00 Dec 12, 2005 page 377 of 1034
REJ09B0254-0500