SH7727 Datasheet, PDF (225/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 5 Cache
31
9 87
21 0
W3 W3
LOAD LOCK
W2 W2
LOAD LOCK
W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit.
When W2LOCK = 1 & W2LOAD = 1 & DSP = 1, the prefetched data will always be loaded
into Way2. In all other conditions the prefetched data will be loaded into the way pointed by
LRU.
W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit.
When W3LOCK = 1 & W3LOAD = 1 & DSP = 1, the prefetched data will always be loaded
into Way3. In all other conditions the prefetched data will be loaded into the way pointed by
LRU.
Note: W2LOAD and W3LOAD should not be set to high at the same time.
Figure 5.3 CCR2 Register Configuration
Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high the cache is locked. The locked
data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be
replaced by tables 5.4 to 5.6.
Table 5.4 LRU and Way Replacement (when W2LOCK=1)
LRU (5–0)
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
1
0
Table 5.5 LRU and Way Replacement (when W3LOCK=1)
LRU (5–0)
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
2
1
0
Rev. 5.00 Dec 12, 2005 page 153 of 1034
REJ09B0254-0500