SH7727 Datasheet, PDF (13/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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303 12.2.5 Individual Memory Control Register
(MCR)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS RASD AMX3 AMX2 AMX1 AMX0 RFSH RMO —
1
0
1
0
DE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS — AMX3 AMX2 AMX1 AMX0 RFSH RMO —
1
0
1
0
DE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 14RAS Precharge Time
(TPC1, TPC0):
… However, the number of cycles inserted
immediately after the precharge all banks
(PALL) command is issued when
performing auto-refresh or the precharge
(PRE) command is issued in bank-active
mode is one fewer than the number of
cycles during normal operation. Do not set
TPC1 to 0 and TPC0 to 0 when in bank-
active mode.
… However, the number of cycles inserted
immediately after the precharge all banks
(PALL) command is issued when
performing auto-refresh is one fewer than
the number of cycles during normal
operation.
Note: * Immediately after the precharge all
banks (PALL) command is issued when
performing auto-refresh or the precharge
(PRE) command is issued in bank-active
mode.
Note: * Immediately after the precharge all
banks (PALL) command is issued when
performing auto-refresh.
304 Bit 7—SDRAM Bank Active (RASD):
Bit 7Reserved:
Specifies whether SDRAM is put into bank- _{This bit is always read as 0. The write}
active mode or auto-precharge mode. The
auto-precharge mode should be used if
value should always be 0.
both area 2 and area 3 are set in SDRAM
space and the bus width is 16 bits.
Bit 7: RASD
0
1
Description
Auto-precharge mode
Bank-active mode
(Initial value) _{Table deleted}
309
12.2.6 PCMCIA Control Register (PCR)
Bits 8, 1, and 0Area6 OE/WE Negate
Address Delay (A6TEH2, A6TEH1, and
A6TEH0):
Bit 8:
A6TEH2
1
Bit 1:
A6TEH1
0
1
Bit 0:
A6TEH0
0
1
0
1
Description
4.5-cycle delay
Reserved
Reserved
Reserved
Bit 8:
A6TEH2
1
Bit 1:
A6TEH1
0
1
Bit 0:
A6TEH0
0
1
0
1
Description
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
Rev. 5.00 Dec 12, 2005 page xiii of lxxii