SH7727 Datasheet, PDF (106/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
other than A0G and A1G in the word mode, lower half of the register is cleared. When it is A0 or
A1, the data is sign-extended to bits 39 to 32 and lower half of it is cleared. When A0G or A1G is
a destination register in the word mode, data is loaded into 8-bit register, but A0 or A1 is not
cleared. In the longword mode, when a destination register is A0 or A1, it is sign-extended to bits
39 to 32.
Tables 2.3 and 2.4 show the data type of registers used in the DSP instructions. Some instructions
cannot use some registers shown in the tables because of instruction code limitation. For example,
PMULS can use A1 for source registers, but cannot use A0. These tables ignore details of the
register selectability.
Table 2.3 Destination Register of DSP Instructions
Guard Bits
Register Bits
Registers
Instructions
39
32 31
16 15
0
A0, A1
DSP
Fixed-point, PSHA,
PMULS
Sign-extended 40-bit result
Integer, PDMSB
Sign-extended 24-bit result Cleared
Logical, PSHL
Cleared
16-bit result Cleared
Data
transfer
MOVS.W
Sign-extended 16-bit data Cleared
MOVS.L
Sign-extended 32-bit data
A0G, A1G Data
transfer
MOVS.W
MOVS.L
Data
Data
No update
No update
X0, X1
Y0, Y1
M0, M1
DSP
Fixed-point, PSHA,
PMULS
Integer, logical,
PDMSB, PSHL
32-bit result
16-bit result Cleared
Data
transfer
MOVX/Y.W, MOVS.W
MOVS.L
16-bit result
32-bit data
Cleared
Rev. 5.00 Dec 12, 2005 page 34 of 1034
REJ09B0254-0500