SH7727 Datasheet, PDF (367/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 8 and 7—Area 5 Burst Enable (A5BST1, A5BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode
are used, set the number of burst transfers.
Bit 8: A5BST1
0
1
Bit 7: A5BST0
0
1
0
1
Description
Access area 5 as ordinary memory
(Initial value)
Burst access of area 5 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
Burst access of area 5 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
Burst access of area 5 (16 consecutive accesses).
Can be used only when bus width is 8.
Bits 6 and 5—Area 6 Burst Enable (A6BST1, A6BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode
are used, set the number of burst transfers.
Bit 6: A6BST1
0
1
Bit 5: A6BST0
0
1
0
1
Description
Access area 6 as ordinary memory
(Initial value)
Burst access of area 6 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
Burst access of area 6 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
Burst access of area 6 (16 consecutive accesses).
Can be used only when bus width is 8.
Rev. 5.00 Dec 12, 2005 page 295 of 1034
REJ09B0254-0500