SH7727 Datasheet, PDF (613/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
The reception margin in the asynchronous mode is given by formula 1.
Formula 1:
M = 0.5 − ¹ − (L − 0.5)F − ^{D − 0.5} (1 + F) × 100%
2N
N
Where:
M = Reception margin (%)
N = Ratio of clock frequency to bit rate (N = 16)
D = Clock duty cycle (D = 0–1.0)
L = Frame length (L = 9–12)
F = Absolute deviation of clock frequency
Assuming values of F = 0, D = 0.5 and N = 372 in formula (1), the reception margin is given by
formula 2.
Formula 2:
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.
Cautions for Clock Synchronous External Clock Mode:
• Set TE = RE = 1 only when the external clock SCK is 1.
• Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed
from 0 to 1.
• When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the
SCK input of the D7 bit in RxD, but it cannot be copied to SCRDR.
Caution for Clock Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is
set to zero 1.5 clocks after the rising edge of the SCK output of the D7 bit in RxD, but it cannot be
copied to SCRDR.
Rev. 5.00 Dec 12, 2005 page 541 of 1034
REJ09B0254-0500