SH7727 Datasheet, PDF (550/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 16 Realtime Clock (RTC)
16.4 Usage Notes
16.4.1 Writing Registers During RTC Count Operation
During the RTC count operation (RCR2 bits 0 = 1), the following registers cannot be written.
RSECCNT, RMICNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, and RYRCNT
To write these registers, the RTC count operation should be stopped.
16.4.2 RTC Periodic Interrupts
Figure 16.6 shows the periodic interrupt function setting flow.
Periodic interrupts can be generated with the period specified by the periodic interrupt enable flag
(PES) in the RTC control register (RCR2). When the time period specified by PES passed, the
periodic interrupt flag (PEF) is set to 1.
PEF is cleared to 0 when PES is set and a periodic interrupt is generated. The periodic interrupt
generation can be checked by reading this bit, but is usually checked by the interrupt function.
Set PES and clear PEF ^{PES is set and PEF is}
cleared in RCR2.
Period set by PES passed
Clears PEF
PEF is cleared to 0.
Figure 16.6 Periodic Interrupt Function Setting
Rev. 5.00 Dec 12, 2005 page 478 of 1034
REJ09B0254-0500