SH7727 Datasheet, PDF (157/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
The correspondence between DSP data transfer operands and registers is shown in table 2.29.
CPU core registers are used as a pointer address that indicates a memory address.
Table 2.29 Correspondence between DSP Data Transfer Operands and Registers
Register
CPU
R0
register _R1
R2 (As2)
R3 (As3)
R4 (Ax0)
R5 (Ax1)
R6 (Ay0)
R7 (Ay1)
R8 (Ix)
R9 (Iy)
DSP
A0
register _A1
M0
M1
X0
X1
Y0
Y1
A0G
A1G
Ax
Ix
Dx
Ay
Iy
Dy
Da
As
Ds
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2.6.4 DSP Operation Instruction Set
DSP operation instructions are instructions for digital signal processing performed by the DSP
unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed
in parallel. The instruction code is divided into an A field and B field; a parallel data transfer
instruction is specified in the A field, and a single or double data operation instruction in the B
field. Instructions can be specified independently, and are also executed independently. The
parallel data transfer instruction specified in the A field is exactly the same as a double data
transfer instruction. The function of the A field—that is, the data transfer instruction field—is
Rev. 5.00 Dec 12, 2005 page 85 of 1034
REJ09B0254-0500