SH7727 Datasheet, PDF (252/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
7.3.2 Interrupt Control Register 0 (ICR0)
The ICR0 is a register that sets the input signal detection mode of the external interrupt input pin
NMI and indicates the input signal level to the NMI pin. This register is initialized to H'0000 or
H'8000 at power-on reset or manual reset, but is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
NMIL
—
—
—
—
—
—
NMIE
Initial value: 0/1*
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Note: * When NMI input is high: 1; when NMI input is low: 0.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
0
1
Description
NMI input level is low
NMI input level is high
Bit 8—NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt
request signal to the NMI is detected.
Bit 8: NMIE
0
1
Description
Interrupt request is detected on the falling edge of NMI input
Interrupt request is detected on rising edge of NMI input
(Initial value)
Bits 14 to 9 and 7 to 0—Reserved: These bits are always read as 0. The write value should
always be 0.
Rev. 5.00 Dec 12, 2005 page 180 of 1034
REJ09B0254-0500