SH7727 Datasheet, PDF (382/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
12.2.7 Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address
bus and is an 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3. SDMR
is undefined after a power-on reset. The register contents are not initialized by a manual reset or
standby mode; values remain unchanged.
Bit: 31 ...................... 12 11 10 9
8
7
6
5
4
3
2
1
0
SDMR address
————————————
Initial value: — ...................... — — — — — — — — — — — — —
R/W: — ...................... — W* W* W W W W W W W W — —
Note: * Depending on the type of synchronous DRAM.
Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If
the value to be set is X and the SDMR address is Y, the value X is written in the synchronous
DRAM mode register by writing in address X + Y. Since, with a 32-bit bus width, A0 of the
synchronous DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is
connected to A3 of the chip, the value actually written to the synchronous DRAM is the X value
shifted two bits right. With a 16-bit bus width, the value written is the X value shifted one bit
right. For example, with a 32-bit bus width, when H'0230 is written to the SDMR register of area
2, random data is written to the address H'FFFFD000 (address Y) + H'08C0 (value X), or
H'FFFFD8C0. As a result, H'0230 is written to the SDMR register. The range for value X is
H'0000 to H'0FFC. When H'0230 is written to the SDMR register of area 3, random data is written
to the address H'FFFFE000 (address Y) + H'08C0 (value X), or H'FFFFE8C0. As a result, H'0230
is written to the SDMR register. The range for value X is H'0000 to H'0FFC.
Rev. 5.00 Dec 12, 2005 page 310 of 1034
REJ09B0254-0500