SH7727 Datasheet, PDF (333/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 10 On-Chip Oscillation Circuits
10.2.2 CPG Pin Configuration
Table 10.1 lists the CPG pins and their functions.
Table 10.1 Clock Pulse Generator Pins and Functions
Pin Name
Symbol I/O Description
Mode control pins MD0
I
Set the clock operating mode.
MD1
I
MD2
I
Crystal I/O pins
XTAL
O
Connects a crystal oscillator.
(clock input pins)
EXTAL I
Connects a crystal oscillator. Also used to input an
external clock.
Clock I/O pin
CKIO
I/O Inputs or outputs an external clock.
Clock Out pin
CKIO2
O
Output external clock. Level can be fixed. Only clock
modes 0, 1, 2 can be supported for this pin.
Capacitor
CAP1
I
Connects capacitor for PLL circuit 1 operation
connection pins
(recommended value 470 pF).
For PLL
CAP2
I
Connects capacitor for PLL circuit 2 operation
(recommended value 470 pF).
10.2.3 CPG Register Configuration
Table 10.2 shows the CPG register configuration.
Table 10.2 Register Configuration
Register Name
Abbreviation R/W Initial Value Address
Access Size
Frequency control register FRQCR
R/W H'0102
H'FFFFFF80 16 bits
CKIO2 Control Register 2 CKIO2CR
R/W H'0000
H'0400023A 16 bits
(H'A400023A)*
Note: * When address translation by the MMU does not apply, the address in parentheses should
be used.
Rev. 5.00 Dec 12, 2005 page 261 of 1034
REJ09B0254-0500