SH7727 Datasheet, PDF (261/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Bit 4—IRQ4 Interrupt Request (IRQ4R): Indicates whether an interrupt request is input to the
IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing
the IRQ4R bit.
Bit 4: IRQ4R
0
1
Description
An interrupt request is not input to IRQ4 pin
An interrupt request is input to IRQ4 pin
(Initial value)
Bit 3—IRQ3 Interrupt Request (IRQ3R): Indicates whether an interrupt request is input to the
IRQ3 pin. When edge detection mode is set for IRQ3, an interrupt request is cleared by clearing
the IRQ3R bit.
Bit 3: IRQ3R
0
1
Description
An interrupt request is not input to IRQ3 pin
An interrupt request is input to IRQ3 pin
(Initial value)
Bit 2—IRQ2 Interrupt Request (IRQ2R): Indicates whether an interrupt request is input to the
IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by clearing
the IRQ2R bit.
Bit 2: IRQ2R
0
1
Description
An interrupt request is not input to IRQ2 pin
An interrupt request is input to IRQ2 pin
(Initial value)
Bit 1—IRQ1 Interrupt Request (IRQ1R): Indicates whether an interrupt request is input to the
IRQ1 pin. When edge detection mode is set for IRQ1, an interrupt request is cleared by clearing
the IRQ1R bit.
Bit 1: IRQ1R
0
1
Description
An interrupt request is not input to IRQ1 pin
An interrupt request is input to IRQ1 pin
(Initial value)
Bit 0—IRQ0 Interrupt Request (IRQ0R): Indicates whether an interrupt request is input to the
IRQ0 pin. When edge detection mode is set for IRQ0, an interrupt request is cleared by clearing
the IRQ0R bit.
Rev. 5.00 Dec 12, 2005 page 189 of 1034
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