SH7727 Datasheet, PDF (384/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source
clock is the external bus clock (BCLK). The RTCNT count clock is CKIO divided by the specified
ratio. The specified ratios are shown below in the normal external bus clock. Before specifying
the CKS2 to CKS0 of RTCST, the RTCOR must be specified.
Bit 5: CKS2
0
1
Bit 4: CKS1
0
1
0
1
Bit 3: CKS0
0
1
0
1
0
1
0
1
Description
Normal external bus clock
Disables clock input
Bus clock (CKIO)/4
CKIO/16
CKIO/64
CKIO/256
CKIO/1024
CKIO/2048
CKIO/4096
(Initial value)
Bit 2—Refresh Count Overflow Flag (OVF): The OVF status flag indicates when the number of
refresh requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS
bit of RTCSR.
Bit 2: OVF
Description
0
RFCR has not exceeded the count limit value set in LMTS
Clear Conditions: When 0 is written to OVF
(Initial value)
1
RFCR has exceeded the count limit value set in LMTS
Set Conditions: When the RFCR value has exceeded the count limit value
set in LMTS*
Note: * Contents don't change when 1 is written to OVF.
Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): OVIE selects whether to suppress
generation of interrupt requests by OVF when the OVF bit of RTCSR is set to 1.
Bit 1: OVIE
0
1
Description
Disables interrupt requests from the OVF
Enables interrupt requests from the OVF
(Initial value)
Rev. 5.00 Dec 12, 2005 page 312 of 1034
REJ09B0254-0500