SH7727 Datasheet, PDF (465/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bit 1—Transfer End (TE): TE is set to 1 when data transfer ends by the count specified in
DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
Before this bit is set to 1, if data transfer ends due to an NMI interrupt, a DMAC address error, or
clearing the DE bit or the DME bit in DMAOR, this bit is not set to 1. Even if the DE bit is set to
1 while this bit is set to 1, transfer is not enabled.
Bit 1: TE
0
1
Description
Data transfer does not end by the count specified in DMATCR (Initial value)
Clear condition: Writing 0 after TE = 1 read at power-on reset or manual reset
Data transfer ends by the specified count
Bit 0—DMAC Enable (DE): DE enables channel operation.
Bit 0: DE
0
1
Description
Disables channel operation
Enables channel operation
(Initial value)
If the auto request is specified in RS3 to RS0, transfer starts when this bit is set to 1. For an
external request or an on-chip module request, transfer starts if a transfer request is generated after
this bit is set to 1. Clearing this bit during transfer can terminate transfer.
Even if the DE bit is set, transfer is not enabled when the TE bit is 1, the DME bit in DMAOR is
0, or the NMIF bit or AE bit in DMAOR is 1.
Rev. 5.00 Dec 12, 2005 page 393 of 1034
REJ09B0254-0500