SH7727 Datasheet, PDF (296/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.3.4 Break on X/Y-Memory Bus Cycle
1. The break condition on X/Y-memory bus cycle is specified only in channel B. If XYE in
BBRB is set to 1, break address and break data on X/Y-memory bus are selected. At this time,
select X-memory bus or Y-memory bus by specifying XYS in BBRB. The Break condition
cannot include both X-memory and Y-memory at the same time. The break condition is
applied to X/Y-memory bus cycle by specifying CPU/data access/read or write/word or no
operand size specification in the break bus cycle register B (BBRB).
2. When X-memory address is selected as the break condition, specify X-memory address in
upper 16 bits in BARB and BAMRB. When Y-memory address is selected, specify Y-memory
address in lower 16 bits. Specification of X/Y-memory data is the same for BDRB and
BDMRB.
8.3.5 Sequential Break
1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break
condition matches after channel A break condition matches. A user break is ignored even if
channel B break condition matches before channel A break condition matches. When channels
A and B condition match at the same time, the sequential break is not issued.
2. In sequential break specification, internal/X/Y bus can be selected and the execution times
break condition can be also specified. For example, when the execution times break condition
is specified, the break condition is satisfied at channel B condition match with BETR = H'0001
after channel A condition match.
8.3.6 Value of Saved Program Counter
The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows
depending on the type of break.
1. When instruction fetch (before instruction execution) is specified as a break condition:
The value of the program counter (PC) saved is the address of the instruction that matches the
break condition. The fetched instruction is not executed, and a break occurs before it.
2. When instruction fetch (after instruction execution) is specified as a break condition:
The PC value saved is the address of the instruction to be executed following the instruction in
which the break condition matches. The fetched instruction is executed, and a break occurs
before the execution of the next instruction.
Rev. 5.00 Dec 12, 2005 page 224 of 1034
REJ09B0254-0500