SH7727 Datasheet, PDF (405/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
SH7727
A14
A13
A12
···
···
A1
CKIO, CKIO2
CKE
CSn
RAS3
CAS
RD/WR
D15
···
···
D0
DQMLU
DQMLL
64M synchronous DRAM
(1M × 16-bit × 4-bank)
A13
A12
A11
···
···
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
···
···
DQ0
DQMU
DQML
Figure 12.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMX3 to AMX0 in MCR.
Table 12.12 shows the relationship between the address multiplex specification bits and the bits
output at the address pins. Table 12.13 shows the relationship between LSI address pins and
synchronous DRAM address pins.
A25 to A17 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it performs
longword address specification. Connection should therefore be made in the following order: with
a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect
pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to pin A1 of
this LSI, then connect pin A1 and pin A2.
Rev. 5.00 Dec 12, 2005 page 333 of 1034
REJ09B0254-0500