SH7727 Datasheet, PDF (35/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

4.5.1 Resets ................................................................................................................... 140
4.5.2 General Exceptions .............................................................................................. 141
4.5.3 Interrupts.............................................................................................................. 146
4.6 Usage Notes ...................................................................................................................... 147
Section 5 Cache.................................................................................................................... 149
5.1 Overview........................................................................................................................... 149
5.1.1 Features................................................................................................................ 149
5.1.2 Cache Structure.................................................................................................... 149
5.1.3 Register Configuration......................................................................................... 151
5.2 Register Description.......................................................................................................... 151
5.2.1 Cache Control Register (CCR) ............................................................................ 151
5.2.2 Cache Control Register 2 (CCR2)........................................................................ 152
5.3 Cache Operation................................................................................................................ 154
5.3.1 Searching the Cache............................................................................................. 154
5.3.2 Read Access ......................................................................................................... 156
5.3.3 Prefetch Operations.............................................................................................. 156
5.3.4 Write Access ........................................................................................................ 156
5.3.5 Write-Back Buffer ............................................................................................... 157
5.3.6 Coherency of Cache and External Memory ......................................................... 157
5.4 Memory-Mapped Cache.................................................................................................... 157
5.4.1 Address Array ...................................................................................................... 157
5.4.2 Data Array............................................................................................................ 158
5.5 Usage Examples................................................................................................................ 160
5.5.1 Invalidating Specific Entries ................................................................................ 160
5.5.2 Reading the Data of a Specific Entry................................................................... 160
Section 6 X/Y Memory...................................................................................................... 161
6.1 Overview........................................................................................................................... 161
6.1.1 Features................................................................................................................ 161
6.2 X/Y Memory Access from the CPU ................................................................................. 162
6.3 X/Y Memory Access from the DSP.................................................................................. 164
6.4 X/Y Memory Access from the DMAC ............................................................................. 164
Section 7 Interrupt Controller (INTC)........................................................................... 165
7.1 Overview........................................................................................................................... 165
7.1.1 Features................................................................................................................ 165
7.1.2 Block Diagram ..................................................................................................... 166
7.1.3 Pin Configuration................................................................................................. 167
7.1.4 Register Configuration......................................................................................... 167
7.2 Interrupt Sources ............................................................................................................... 169
Rev. 5.00 Dec 12, 2005 page xxxv of lxxii