SH7727 Datasheet, PDF (379/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bit 15—Area 6 Wait Control (A6W3): The A6W3 bit specifies the number of inserted wait
states for area 6 combined with bits A6W2 to A6W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0 when area 6 is not set to PCMCIA.
Top Cycle
A6W3
0
A6W2
0
1
A6W1
0
1
0
1
A6W0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Inserted
Wait State
0
1
2
3
4
6
8
10
(Initial value)
12
14
18
22
26
30
34
38
WAIT Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Burst Cycle
Number of
States per
One-data
Transfer
WAIT Pin
2
Enabled
2
Enabled
3
Enabled
4
Enabled
5
Enabled
7
Enabled
9
Enabled
11
Enabled
13
Enabled
15
Enabled
19
Enabled
23
Enabled
27
Enabled
31
Enabled
35
Enabled
39
Enabled
Bit 14—Area 5 Wait Control (A5W3): The A5W3 bit specifies the number of inserted wait
states for area 5 combined with bits A5W2 to A5W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0 when area 5 is not set to PCMCIA.
The relationship between the setting value and the number of waits is the same as A6W3.
Bits 13 and 12—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.00 Dec 12, 2005 page 307 of 1034
REJ09B0254-0500