SH7727 Datasheet, PDF (1018/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 32 Electrical Characteristics
32.3.2 Control Signal Timing
Table 32.9 Control Signal Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Min
Max
Figure
RESETP pulse width
RESETP setup time^*1
tRESPW
20^*2
—
tRESPS
23
—
tcyc 32.13
ns
32.14
RESETP hold time
RESETM pulse width
tRESPH
2
—
tRESMW
12^*3
—
ns
tcyc
RESETM setup time
tRESMS
3
—
ns
RESETM hold time
tRESMH
34
—
ns
BREQ setup time
tBREQS
10
—
ns
32.15
BREQ hold time
NMI setup time ^*1
tBREQH
3
—
ns
tNMIS
10
—
ns
32.14
NMI hold time
IRQ5–IRQ0 setup time ^*1
tNMIH
4
—
ns
tIRQS
10
—
ns
IRQ5–IRQ0 hold time
tIRQH
4
—
ns
BACK delay time
tBACKD
—
10
ns
32.15
STATUS1, STATUS0 delay time
tSTD
—
16
ns
32.16
Bus tri-state delay time 1
tBOFF1
0
15
ns
Bus tri-state delay time 2
tBOFF2
0
15
ns
Bus buffer-on time 1
tBON1
0
15
ns
Bus buffer-on time 2
tBON2
0
15
ns
Notes: 1. RESETP, NMI and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
clock fall when the setup shown is used. When the setup cannot be used, detection
can be delayed until the next clock falls. When using as IRL, please observe the setup
time.
2. In the standby mode, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100 µs).
When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 µs).
3. In the standby mode, tRESMW = tOSC2 (10 ms). In the sleep mode, RESETM must be kept
low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is
changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH).
Rev. 5.00 Dec 12, 2005 page 946 of 1034
REJ09B0254-0500