SH7727 Datasheet, PDF (242/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the
pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask
after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
It is necessary for an edge input interrupt detection to input a pulse width more than two-cycle
width by P clock basis.
With level detection, the level must be maintained until the interrupt is accepted and the CPU
starts interrupt handling.
The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by IRQ interrupt
processing.
Interrupts IRQ5 to IRQ0 can be used to wake the chip up from the software standby mode (but
only when the RTC 32 kHz oscillator is used).
In this case, the priority level of the interrupt to be used must be higher than the level of bits I3 to
I0 in the SR register.
Notes: The following cautions apply when IRQ edge detection is used:
1. If an IRQ edge is input immediately before the CPU enters the standby mode (between
when the CPU executes the SLEEP instruction and when STATUS0 goes high), the
interrupt may not be detected properly. After this, if the IRQ edge is input again after
STATUS0 goes high, the interrupt will be detected.
2. If an IRQ edge is input while the frequency is changing due to a change in the value of
the STC bit in the FRQCR register (during the count by WDT), the interrupt may not
be detected properly. If the IRQ edge is input again after the WDT count completes,
the interrupt will be detected.
7.2.3 IRL Interrupts
IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the higher level
indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level
interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request
(interrupt priority level 0). Figure 7.2 shows an example of an IRL interrupt connection. Table 7.3
shows IRL pins and interrupt levels.
Rev. 5.00 Dec 12, 2005 page 170 of 1034
REJ09B0254-0500