SH7727 Datasheet, PDF (435/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
CKIO
T1
T2 Twait T1
T2 Twait T1
T2
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Area m read
Area n space read
Area n space write
Area m inter-access wait specification Area n inter-access wait specification
Figure 12.33 Waits between Access Cycles
12.3.8 Bus Arbitration
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not
released during burst transfers for cache fills or TAS instruction execution between the read cycle
and write cycle. Bus arbitration is not executed in multiple bus cycles that are generated when the
data bus width is shorter than the access size; i.e. in the bus cycles when longword access is
executed for the 8-bit memory. At the negation of BREQ, BACK is negated and bus use is
restarted. See Appendix A.1, Pin Functions, for the pin state when the bus is released.
Rev. 5.00 Dec 12, 2005 page 363 of 1034
REJ09B0254-0500