SH7727 Datasheet, PDF (598/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Multiprocessor Serial Data Reception:
Figure 17.15 shows a sample flow chart for multiprocessor serial data reception. After enabling
the SCI reception, receive multiprocessor serial data following the procedure shown below:
Start reception
Set MPIE bit in SCSCR to 1 (1)
Read ORER and FER
bits in SCSSR
FER = 1 or ORER = 1?
Yes
No
Read RDRF bit in SCSSR (2)
No
RDRF = 1?
Yes
Read receive data in SCRDR
No
Is ID the
station’s ID?
Yes
Read ORER and FER
bits in SSCSR
FER = 1 or ORER = 1?
Yes
No
Read RDRF bit in SCSSR (4)
RDRF = 1?
No
Yes
Read receive data in SCRDR
(1) ID receive cycle:
Set the MPIE bit in the serial control
register (SCSCR) to 1.
(2) SCI status check and compare to
ID reception:
Read the serial status register
(SCSSR), check that RDRF is set
to 1, then read data from the
receive data register (SCRDR) and
compare with the processor's own
ID. If the ID does not match the
receive data, set MPIE to 1 again
and clear RDRF to 0. If the ID
matches the receive data, clear
RDRF to 0.
(3) SCI status check and data
receiving:
Read SCSSR, check that RDRF is
set to 1, then read data from the
receive data register (SCRDR).
(4) Receive error processing and break
detection:
If a receive error occurs, read the
ORER and FER bits in SCSSR to
identify the error. After executing
the necessary error processing,
clear both ORER and FER to 0.
Receiving cannot resume if ORER
or FER remain set to 1. When a
framing error occurs, the RxD pin
can be read to detect the break
state.
No
All data received?
Yes
Clear RE bit in SCSCR to 0
(3)
Error processing
End reception
Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 5.00 Dec 12, 2005 page 526 of 1034
REJ09B0254-0500