SH7727 Datasheet, PDF (692/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.2.8 Status Register (SISTR)
This register shows states of SIOF. Each bit of this register becomes interrupt source when 1 is set
to corresponding register of SIIER register.
This register is initialized at power on reset or software reset.
Bit: 15
14
13
12
11
10
9
8
— TCRDY TFEMP TDREQ — RCRDY RFFUL RDREQ
Initial value:
0
0
0
0
0
0
0
0
R/W: R*
R*
R*
R*
R*
R*
R*
R*
Bit:
7
6
5
4
3
2
1
—
—
—
FSERR TFOVR TFUDR RFUDR
Initial value:
0
0
0
0
0
0
0
R/W: R*
R*
R*
R/W
R/W
R/W
R/W
Note: * 0 should be written into these bits. Otherwise the operation is unpredictable.
0
RFOVR
0
R/W
Bits 15, 11, and 7 to 5—Reserved
Bit 14—Transmit Control Data Ready (TCRDY): This bit displays condition of SITCR
register. SIOF clears when any value is written to SITCR register. This bit becomes effective
when 1 is written to TXE bit of SICTR register. SIOF issues control interrupt if interrupt issuing is
allowed for this bit. Once any data are written to SICTR register with 0 of TCRDY bit, new data is
overwritten to original data and original data of TXD_SIO will be lost.
Note: When using this bit, refer to note 2 in section 20.4, Notes on Use.
Bit 14: TCRDY
0
1
Description
Disable writing into SITCR register
Enable writing into SITCR register
(Initial value)
Bit 13—Transmit FIFO Empty (TFEMP): This bit is showing condition, SIOF clear by writing
to SITDR register. This bit becomes effective when 1 is written to the TXE bit of SICTR register.
SIOF issues control interrupt if interrupt issuing is allowed by this bit.
Rev. 5.00 Dec 12, 2005 page 620 of 1034
REJ09B0254-0500