SH7727 Datasheet, PDF (722/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
(5) A Case of 16 bits Stereo (No.2)
L/R method, rising edge sampling and Lch.transmit data are assigned to slot No. 0, Lch. receive
data are assigned to slot No.1, Lch. receive data are assigned to slot No. 2, Rch. receive data is
assigned to slot No. 3, and frame length is 64 bits.
1 frame
SCK_SIO
SIOFSYN
TXD_SIO
Lch. DATA
Rch. DATA
RXD_SIO
Slot No.0
No delay
Lch. DATA
Slot No.1
Slot No.2
Rch. DATA
Slot No.3
Setting: TRMD = 01, REDG = 1,
TDLE = 1, TDLA3 to TDLA0 = 0000,
RDLE = 1, RDLA3 to RDLA0 = 0001,
CD0E = 0, CD0A3 to CD0A0 = 0000,
FL = 1101 (frame length 64 bits),
TDRE = 1, TDRA3 to TDRA0 = 0010,
RDRE = 1, RDRA3 to RDRA0 = 0011,
CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 20.17 Transmit or Receive Timing (16 bits stereo—2)
(6) A Case of 16 bits Stereo (No. 3)
Sync pulse method, falling edge sampling and Lch. data are assigned to slot No. 0, Rch. data is
assigned to slot No. 2, control ch. data 0 is assigned to slot No. 1, control ch. data 0 is assigned to
slot No. 3, and frame length is 128 bits.
1 frame
SCK_SIO
SIOFSYN
TXD_SIO
RXD_SIO
Lch. DATA Control ch. 0 Rch. DATA Control ch. 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
1 bit delay
Setting: TRMD = 00 or 10, REDG = 0,
TDLE = 1,
TDLA3 to TDLA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000,
CD0E = 1,
CD0A3 to CD0A0 = 0001,
FL = 1110 (frame length 128 bits),
TDRE = 1, TDRA3 to TDRA0 = 0010,
RDRE = 1, RDRA3 to RDRA0 = 0010,
CD1E = 1, CD1A3 to CD1A0 = 0011
Figure 20.18 Transmit or Receive Timing (16 bits stereo—3)
Rev. 5.00 Dec 12, 2005 page 650 of 1034
REJ09B0254-0500