SH7727 Datasheet, PDF (736/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
21.2.4 AFEIF Status Register 1 and 2 (ASTR1, ASTR2)
ASTR is the control register for AFEIF, and composed of ASTR1 and ASTR2. ASTR1 is mainly
used for transmit/receive FIFO interrupt control commands. ASTR2 is used for DAA interrupt
control commands. See section 21.3.1, Interrupt Timing for more detail about interrupt handling.
(1) AFEIF Status Register 1 (ASTR1)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
TFEM RFFM THEM RHFM
Initial value:
0
0
0
0
1
1
1
1
R/W: R/W
R
R
R
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
TFE
RFF
THE
RHF
Initial value:
0
0
0
0
1
0
1
0
R/W:
R
R
R
R
R
R
R
R
ASTR1 is composed by interrupt status flags (4 bits) relating transmit/receive FIFO and mask
flags (4 bits) for transmit/receive FIFO interrupt signal. Status flag displays full/empty interrupt
status of transmit/receive FIFO and half size interrupt status for FIFO. FIFO empty (TFE) and
FIFO half size interrupt(THE) shows “1” as initial value, because transmit FIFO is empty after
power on reset. These interrupt flags are to be cleared with the data write / read action to FIFO
from CPU.
Each interrupt mask flag is able to prohibit interrupt generation of each interrupt that indicated in
interrupt status flag. Every mask bits are automatically set when TE or RE bit are modified to 1.
TFEM and THEM are 1 when TE = 0. RFFM and RHFM are “1” when RE = “0”. Each mask bit
are reset as 1.
Bits 15 to 12 and 7 to 4—Reserved
Bit 11—Tx FIFO Empty Interrupt Mask (TFEM)
Bit 11: TFEM
0
1
Description
TFE Interrupt enable
TFE interrupt masked
(Initial value)
Rev. 5.00 Dec 12, 2005 page 664 of 1034
REJ09B0254-0500