SH7727 Datasheet, PDF (1029/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

32.3.6 Synchronous DRAM Timing
Section 32 Electrical Characteristics
CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
Tr
Tc1
Tc2
(Tpc)
t_AD
Row address
t_AD
t_AD
t_AD
Row address
t_AD
t_AD
Read A
command
Row address
t_CSD1
Column address
t_AD
t_AD
t_CSD1
t_RWD
t_RWD
t_RASD2
t_RASD2
t_CASD2
t_CASD2
t_DQMD
t_DQMD
t_RDS2 t_RDH2
t_BSD
t_BSD
CKE
DACKn
t_DAKD1
(High)
t_DAKD1
Figure 32.23 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)
Rev. 5.00 Dec 12, 2005 page 957 of 1034
REJ09B0254-0500