SH7727 Datasheet, PDF (733/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
Bits 4 to 2—FIFO Interrupt Size Set 2 to 0 (FFSZ2 to FFSZ0): Specifies the size of FIFO.
FIFO size to generate interrupt (TFE, RFF, THE, and RHF) is assigned as follows:
Bit 4:
FFSZ2
0
1
Bit 3:
FFSZ1
0
1
0
1
Bit 2:
FFSZ0
0
1
0
1
0
1
0
1
FIFO Size
128
64
32
16
8
4
2
96
Description
TFE/RFF
THE/RHF
128 empty/full 64 empty/full
64 empty/full 32 empty/full
32 empty/full 16 empty/full
16 empty/full 8 empty/full
8 empty/full
4 empty/full
4 empty/full
2 empty/full
2 empty/full
1 empty/full
96 empty/full 48 empty/full
(Initial value)
Bit 1—Tx Enable (TE)
Bit 1: TE
0
1
Description
Transmit operation is disabled. The READ pointer of FIFO is stacked to the
first address. WRITE pointer is reset when 0 is written to this bit. TFEM and
THEM bits in ASTR1 is set to 1 at that time.
(Initial value)
Transmit operation is enabled.
Bit 0—Rx Enable (RE)
Bit 0: RE
0
1
Description
Receive operation is disabled. The WRITE/READ pointer is fixed to the first
address. RFFM and RHFM bits in ASTR1 is set to 1 at that time.
Receive operation is enabled
Rev. 5.00 Dec 12, 2005 page 661 of 1034
REJ09B0254-0500