SH7727 Datasheet, PDF (447/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
Bits 6 to 3—Address Multiplex (AMX3 , AMX2, AMX1, AMX0): The AMX bits specify
address multiplexing for synchronous DRAM.
Bit6: Bit5: Bit 4: Bit 3:
AMX3 AMX2 AMX1 AMX0 Description
1
1
0
1
When using a 16-bit bus width, the row address begins with
A10. When using a 32-bit bus width, it begins with A11.
(The A10 value is output at A1 when the row address is
output. 4M × 16-bit × 4-bank products)
1
0
When using a 16-bit bus width, the row address begins with
A11.
(The A11 value is output at A1 when the row address is
output. 8M × 16-bit × 4-bank products)*¹
0
1
0
0
When using a 16-bit bus width, the row address begins with
A9. When using a 32-bit bus width, it begins with A10.
(The A9 value is output at A1 when the row address is
output. 1M × 16-bit × 4-bank products)
1
When using a 16-bit bus width, the row address begins with
A10. When using a 32-bit bus width, it begins with A11.
(The A10 value is output at A1 when the row address is
output. 2M × 8-bit products)
0
The row address begins with A11 when bus width is 32 bit. *²
(The A11 value is output at A1 when the row address is
output. 4M × 8-bit × 4-bank products)
1
1
When using a 16-bit bus width, the row address begins with
A9. When using a 32-bit bus width, it begins with A10.
(The A9 value is output at A1 when the row address is output.
512K × 32-bit × 4-bank products) *²
0
0
0
Reserved. AMX3 to AMX0 must be set to *1*** before
accessing synchronous DRAM memory.
(Initial value)
Other values
Reserved (Illegal setting)
Notes: 1. Can be set only when using a 16-bit bus width.
2. Can be set only when using a 32-bit bus width.
Bits 2 and 1—Not referenced
Bit 0—Reserved: This bit is always read as 0 and should only be written with 0.
Rev. 5.00 Dec 12, 2005 page 375 of 1034
REJ09B0254-0500