SH7727 Datasheet, PDF (565/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Bit 4: RE
Description
0
Receiver disabled^*1
(Initial value)
1
Receiver enabled^*2
Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These
flags retain their previous values.
2. Serial reception starts when a start bit is detected in the asynchronous mode, or
synchronous clock input is detected in the clock synchronous mode. Select the receive
format in the SCSMR before setting RE to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is
ignored in the clock synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
Description
0
Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clear conditions]
1. When MPIE is cleared to 0
2. When the multiprocessor bit (MPB) is set to 1 in receive data
1
Multiprocessor interrupts are enabled*
Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI),
and setting of the RDRF, FER, and ORER status flags in the serial status register
(SCSSR) are disabled until data with a multiprocessor bit of 1 is received.
Note: * The SCI does not transfer receive data from the SCRSR to the SCRDR, does not detect
receive errors, and does not set the RDRF, FER, and ORER flags in the serial status
register (SCSSR). When it receives data that includes MPB = 1, the SCSSR’s MPB flag is
set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if
the TIE and RIE bits in the SCSCR are set to 1), and allows the FER and ORER bits to be
set.
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) requests are disabled*
(Initial value)
1
Transmit-end interrupt (TEI) requests are enabled*
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register
(SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end
(TEND) bit to 0, or by clearing the TEIE bit to 0.
Rev. 5.00 Dec 12, 2005 page 493 of 1034
REJ09B0254-0500