SH7727 Datasheet, PDF (129/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Instruction Format
d type
15
0
xxxx xxxx dddd dddd
d12 type
15
0
xxxx dddd dddd dddd
Source
Operand
Destination
Operand
Sample Instruction
dddddddd:
R0 (register direct) MOV.L @@(disp,GBR),R0
GBR indirect with
displacement
R0 (register
direct)
dddddddd: GBR MOV.L @R0,@(disp,GBR)
indirect with
displacement
dddddddd:
PC-relative with
displacement
R0 (register direct) MOVA @(disp,PC),R0
dddddddd:
—
PC-relative
BF label
dddddddddddd: —
PC-relative
BRA label
(label=disp+PC)
nd8 type
15
xxxx nnnn dddd
0
dddd
dddddddd:
PC-relative with
displacement
nnnn: register
direct
MOV.L @(disp,PC),Rn
i type
iiiiiiii:
15
0 ^immediate
xxxx xxxx i i i i i i i i
iiiiiiii:
immediate
iiiiiiii:
immediate
ni type
15
iiiiiiii:
0 ^immediate
xxxx nnnn i i i i i i i i
Indexed GBR
indirect
AND.B #imm,@(R0,GBR)
R0 (register direct) AND #imm,R0
—
TRAPA #imm
nnnn: register
direct
ADD #imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 5.00 Dec 12, 2005 page 57 of 1034
REJ09B0254-0500