SH7727 Datasheet, PDF (59/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 19.2 SCPT[4]/TxD2 Pin................................................................................................. 567
Figure 19.3 SCPT[4]/RxD2 Pin................................................................................................. 568
Figure 19.4 Sample SCIF Initialization Flowchart .................................................................... 592
Figure 19.5 Sample Serial Transmission Flowchart .................................................................. 593
Figure 19.6 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 595
Figure 19.7 Example of Operation Using Modem Control (CTS)............................................. 595
Figure 19.8 Sample Serial Reception Flowchart (1).................................................................. 596
Figure 19.9 Sample Serial Reception Flowchart (2).................................................................. 597
Figure 19.10 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 599
Figure 19.11 Example of Operation Using Modem Control (RTS)............................................. 599
Figure 19.12 Receive Data Sampling Timing in Asynchronous Mode ....................................... 602
Section 20 Serial IO (SIOF)
Figure 20.1 SIOF Block Diagram.............................................................................................. 606
Figure 20.2 Serial Clock Supply System ................................................................................... 630
Figure 20.3 SIOF Serial Data Synchronized Timing................................................................. 631
Figure 20.4 SIOF Transmit or Receive Timing ......................................................................... 632
Figure 20.5 Transmit or Receive Data Bit Alignment ............................................................... 634
Figure 20.6 Control Data Bit Alignment ................................................................................... 636
Figure 20.7 Control Data Interface (Slot Position) .................................................................... 637
Figure 20.8 Control Data Interface (Secondary FS) .................................................................. 638
Figure 20.9 Example of Transmit Operation in Master ............................................................. 641
Figure 20.10 Example of Receive Operation in Master............................................................... 642
Figure 20.11 Example of Transmit Operation in Slave ............................................................... 643
Figure 20.12 Example of Receive Operation in Slave................................................................. 644
Figure 20.13 Transmit or Receive Timing (8 bits monaural—1) ................................................ 648
Figure 20.14 Transmit or Receive Timing (8 bits monaural—2) ................................................ 648
Figure 20.15 Transmit or Receive Timing (16 bits monaural—1) .............................................. 649
Figure 20.16 Transmit or Receive Timing (16 bits stereo—1).................................................... 649
Figure 20.17 Transmit or Receive Timing (16 bits stereo—2).................................................... 650
Figure 20.18 Transmit or Receive Timing (16 bits stereo—3).................................................... 650
Figure 20.19 Transmit or Receive Timing (16 bits monaural—2) .............................................. 651
Section 21 Analog Front End Interface (AFEIF)
Figure 21.1 Block Diagram of AFE Interface ........................................................................... 658
Figure 21.2 FIFO Interrupt Timing............................................................................................ 672
Figure 21.3 Ringing Interrupt Occurrence Timing .................................................................... 672
Figure 21.4 Interrupt Generator ................................................................................................. 673
Figure 21.5 AFE Serial Interface............................................................................................... 673
Figure 21.6 AFE Control Sequence........................................................................................... 674
Rev. 5.00 Dec 12, 2005 page lix of lxxii