SH7727 Datasheet, PDF (287/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.2.9 Break Control Register (BRCR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — BAS BAS — — — —
MA MB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R
R
R
Bit: 15 14 13 12 11 10 9
SCM SCM SCM SCM PCTE PCBA —
FCA FCB FDA FDB
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
8
7
6
5
— DBEB PCBB —
0
0
0
0
R R/W R/W R
4
3
2
— SEQ —
0
0
0
R R/W R
1
0
— ETBE
0
0
R R/W
BRCR sets the following conditions:
1. Channels A and B are used in two independent channels condition or under the sequential
condition.
2. A break is set before or after instruction execution.
3. A break is set by the number of execution times.
4. Determine whether to include data bus on channel B in comparison conditions.
5. Enable PC trace.
6. Enable the ASID check.
The break control register (BRCR) is a 32-bit read/write register that has break conditions match
flags and bits for setting a variety of break conditions.
A power-on reset initializes BRCR to H'00000000.
Bits 31 to 22—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break
ASID7 to ASID0 (BASA7 to BASA0) set in BASRA are masked or not.
Bit 21: BASMA Description
0
All BASRA bits are included in break condition, and ASID is checked
(Initial value)
1
No BASRA bits are included in break condition, and ASID is not checked
Rev. 5.00 Dec 12, 2005 page 215 of 1034
REJ09B0254-0500