SH7727 Datasheet, PDF (67/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 9.4 Register States in Standby Mode............................................................................ 244
Section 10 On-Chip Oscillation Circuits
Table 10.1 Clock Pulse Generator Pins and Functions............................................................. 261
Table 10.2 Register Configuration ........................................................................................... 261
Table 10.3 Clock Operating Modes.......................................................................................... 262
Table 10.4 Available Combination of Clock Mode and FRQCR Values................................. 264
Table 10.5 Register Configuration ........................................................................................... 272
Section 11 Extend Clock Pulse Generator for USB (EXCPG)
Table 11.1 Pin Configuration ................................................................................................... 280
Table 11.2 Register Configuration ........................................................................................... 280
Section 12 Bus State Controller (BSC)
Table 12.1 Pin Configuration ................................................................................................... 286
Table 12.2 Register Configuration ........................................................................................... 288
Table 12.3 Physical Address Space Map ................................................................................. 290
Table 12.4 Correspondence between External Pins (MD4 and MD3)
and Memory bus width in area0 ............................................................................. 291
Table 12.5 SH7727 and PCMCIA Pins .................................................................................... 292
Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment .......................... 316
Table 12.7 16-Bit External Device/Big Endian Access and Data Alignment .......................... 317
Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment ............................ 318
Table 12.9 32-Bit External Device/Little Endian Access and Data Alignment........................ 319
Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment........................ 320
Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment.......................... 321
Table 12.12 Relationship between Synchronous DRAM type, bus width and AMX ................ 334
Table 12.13 Relationship between LSI Address Pins and Synchronous DRAM Address Pins . 335
Section 13 Li Bus State Controller (LBSC)
Table 13.1 Register Configuration ........................................................................................... 367
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1 Pin Configuration ................................................................................................... 382
Table 14.2 DMAC Registers .................................................................................................... 382
Table 14.3 Selecting External Request Modes with the RS Bits.............................................. 400
Table 14.4 Selection of On-Chip Module Request Modes Using RS3 to RS0 Bits ................. 401
Table 14.5 DMA Transfers ...................................................................................................... 405
Table 14.6 Relationship of Request Modes and Bus Modes .................................................... 416
Table 14.7 Register Configuration ........................................................................................... 432
Rev. 5.00 Dec 12, 2005 page lxvii of lxxii