SH7727 Datasheet, PDF (561/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
17.2.5 Serial Mode Register (SCSMR)
Bit:
7
6
5
C/A CHR
PE
Initial value:
0
0
0
R/W: R/W R/W R/W
4
3
2
1
0
O/E STOP MP CKS1 CKS0
0
0
0
0
0
R/W R/W R/W R/W R/W
The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR.
The SCSMR is initialized to H'00 by a reset or in standby and module standby modes.
Bit 7—Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or
clock synchronous mode.
Bit 7: C/A
0
1
Description
Asynchronous mode
Clock synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode.
In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
Description
0
Eight-bit data
(Initial value)
1
Seven-bit data*
Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit data register is not
transmitted.
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
Rev. 5.00 Dec 12, 2005 page 489 of 1034
REJ09B0254-0500