SH7727 Datasheet, PDF (112/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
2.2.3 Data Format in Memory
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address, but an address error will occur if the word data starting from an address other
than 2n or longword data starting from an address other than 4n is accessed. In such cases, the data
accessed cannot be guaranteed (figure 2.11).
Address A
Address A + 4
Address A + 8
Address A + 1 Address A + 3 Address A + 11 Address A + 9
Address A
Address A + 2
Address A + 10 Address A + 8
31
23
15
7
0
31
23
15
7
0
Byte 0 Byte 1 Byte 2 Byte 3
Byte 3 Byte 2 Byte 1 Byte 0
Word 0
Word 1
Word 1
Word 0
Longword
Longword
Address A + 8
Address A + 4
Address A
Big-endian mode
Little-endian mode
Figure 2.11 Byte, Word, and Longword Alignment
As the data format, either big endian or little endian byte order can be selected, according to the
MD5 pin at reset. When MD5 is low at reset, the processor operates in big endian. When MD5 is
high at reset, the processor operates in little endian.
2.3 Features of CPU Core Instructions
The CPU core instructions are RISC-type instructions with the following features:
Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code
efficiency.
One Instruction per State: Pipelining is used, and basic instructions can be executed in one state.
At 160-MHz operation, one state is 6.25 ns.
Data Size: The basic data size for operations is longword. Byte, word, or longword can be
selected as the memory access size. Memory byte or word data is sign-extended and operated on
as longword data. Immediate data is sign-extended to longword size for arithmetic operations or
zero-extended to longword size for logical operations.
Rev. 5.00 Dec 12, 2005 page 40 of 1034
REJ09B0254-0500