SH7727 Datasheet, PDF (745/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
(4) Interrupt Generator Circuit
Interrupt is generated as is shown in figure 21.4. That is, AFEIFI signal is generated by
performing OR operation on the four signals from ASTR1 in FIFO interrupt control and the two
signals from ASTR2 in DAA interrupt control, and then sent out to INTC as one interrupt signal.
ASTR1
INT. mask
(FIFO cont.)
INT. factor
4
4
4
ASTR2
(DAA cont.)
2
2
2
INT. mask INT. factor
Figure 21.4 Interrupt Generator
AFEIFI
21.3.2 AFE Interface
(1) Serial Data Transfer Specification
The specification for serial data transfer is base on that of STLC7550, which is an AFE
manufactured by ST microelectronics. STLC7550 has a self-oscillation mode, and flame
synchronous signal AFE_FS used for serial transfer and serial bit clock AFE_SCLK are supplied
by AFE. Figure 21.5 shows the serial transfer interface. After outputting the valid data,
AFE_TXOUT holds the value of LSB.
Sampling period
AFE_FS
AFE_SCLK
AFE_TXOUT
MSB
LSB
AFE_RXIN
Figure 21.5 AFE Serial Interface
Rev. 5.00 Dec 12, 2005 page 673 of 1034
REJ09B0254-0500