SH7727 Datasheet, PDF (448/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
13.2 LBSC Operation
13.2.1 Bus Sharing Architecture
LCDC and USB Host Controller can share the system memory with CPU and DMA Controller, so
these bus masters are able to work without any independent external memory and have huge
available memory space up to 64 Mbyte at area 3.
Since each LCDC, USB Host Controller, CPU, and DMA Controller can access area 3
individually. Set addresses for each controller to avoid address sharing.
13.2.2 Usable System Memory
LBSC works at below memories.
Memory area
Memory type
Bus width
Burst length
Area3
Synchronous DRAM
16 or 32 bits
1 to 4 burst (USBH)
4 to 32 burst (LCDC) with 32-bit bus width, 8 to 64
burst (LCDC) with 16-bit bus width
13.2.3 Bus Arbitration
LBSC accepts a request that comes from LCDC or USB Host at a same time without any
prioritization to each module. LBSC tries to get bus right from BSC at any time when it get a
request from LCDC or USB Host. Once BSC gives LBSC a right, LCDC or BSC can access
external memory directly. The arbiter of LBSC gives a bus right to LCDC or USB Host as even.
13.2.4 LCDC Li Bus Access
While displaying images, the LCDC continuously reads data from the system memory with a 32
burst length. The LCDC burst length is specified by a register in the LCDC. If the data length is
shorter than 32 burst length, such as the case for the edge of LCD panel, the LCDC uses a shorter
burst length.
Rev. 5.00 Dec 12, 2005 page 376 of 1034
REJ09B0254-0500