SH7727 Datasheet, PDF (364/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond
to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0
addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the
address space obtained by adding to it H'20000000 × n (n = 1 to 6). The address range for area 7,
which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 7) corresponding to the area 7
shadow space is reserved, so do not use it.
12.1.6 PC Card Support
The Bus Controller of this LSI supports protocol signals of PCMCIA standard interface
specifications in physical space areas 5 and 6 as another SH3 Series.
PC Card Bus signal (CEIA,CE2A,CE1B,CE2B,IOIS16) are supported for PC Card Bus Protocol
as same as SH7708/SH7709/SH7729 series.
Dynamic bus sizing of I/O bus width is supported only in the little endian made.
Table 12.5 SH7727 and PCMCIA Pins
SH7727
CE1A
CE1B
CE2A
CE2B
WE
RD
IOIS16
ICIORD
ICIOWR
A25–A0
D15–D0
PCMCIA
CE1
CE1
CE2
CE2
WE/PGM
OE
WP/IOIS16
IORD
IOWR
A25–A0
D15–D0
Rev. 5.00 Dec 12, 2005 page 292 of 1034
REJ09B0254-0500