SH7727 Datasheet, PDF (684/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.2.3 Transmit Data Assign Register (SITDAR)
This register specifies the data assignment of transmit data in each transmit frame. This register is
initialized in power on reset or software reset.
Bit: 15
14
13
12
11
10
9
8
TDLE
—
—
—
TDLA3 TDLA2 TDLA1 TDLA0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R/W
R/W
R/W
R/W
Bit:
7
6
5
TDRE TLREP
—
Initial value:
0
0
0
R/W: R/W
R/W
R
4
3
2
1
0
—
TDRA3 TDRA2 TDRA1 TDRA0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
Bits 14 to 12, 5, and 4—Reserved
Bit 15—Transmit Data for Left Channel Enable (TDLE)
Bit 15: TDLE
0
1
Description
Disable data transmitting of left channel data
Enable data transmitting of left channel data
(Initial value)
Bits 11 to 8—Transmit Data for Left Channel Assignment (TDLA3 to TDLA0): The slot
assignment of transmit data for Left channel in transmit frame is specified from 0000(0: initial
value) to 1110(14) by this register. The transmit data for left channel is set in bits SITDL 15 to
SITDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits TDLA3 to TDLA0.
Bit 7—Transmit Data for Right Channel Enable (TDRE)
Bit 7: TDRE
0
1
Description
Disable data transmitting of right channel data
Enable data transmitting of right channel data
(Initial value)
Rev. 5.00 Dec 12, 2005 page 612 of 1034
REJ09B0254-0500