SH7727 Datasheet, PDF (388/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
12.3 BSC Operation
12.3.1 Endian/Access Size and Data Alignment
This LSI supports both big endian, in which the 0 address is the most significant byte in the byte
data, and little endian, in which the 0 address is the least significant byte. This switchover is
designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-on reset,
big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and long word) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device's data width and endian.
The access unit must also be matched to the device's bus width. This also means that when
longword data is read from a byte-width device, the read operation must happen 4 times. In this
LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit.
Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment
Operation
D31 to
D24
Byte access Data
at 0
7 to 0
Byte access —
at 1
Byte access —
at 2
Byte access —
at 3
Word access Data
at 0
15 to 8
Word access —
at 2
Longword Data
access at 0 31 to 24
Data Bus
D23 to D15 to
D16
D8
—
—
Data
7 to 0
—
—
—
Data
7 to 0
—
Data
7 to 0
—
Data
23 to 16
—
Data
15 to 8
Data
15 to 8
D7 to
D0
—
—
—
Data
7 to 0
—
Data
7 to 0
Data
7 to 0
WE3,
DQMUU
Assert
Strobe Signals
WE2, WE1,
DQMUL DQMLU
WE0,
DQMLL
Assert
Assert
Assert
Assert Assert
Assert Assert
Assert Assert Assert Assert
Rev. 5.00 Dec 12, 2005 page 316 of 1034
REJ09B0254-0500