SH7727 Datasheet, PDF (360/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Table 12.2 Register Configuration
Name
Abbr.
R/W Initial Value* Address
Bus Width
Bus control register 1
BCR1
R/W H'0000
H'FFFFFF60 16
Bus control register 2
BCR2
R/W H'3FF0
H'FFFFFF62 16
Wait state control register 1
WCR1 R/W H'3FF3
H'FFFFFF64 16
Wait state control register 2
WCR2 R/W H'FFFF
H'FFFFFF66 16
Individual memory control
register
MCR
R/W H'0000
H'FFFFFF68 16
PCMCIA control register
PCR
R/W H'0000
H'FFFFFF6C 16
Refresh timer control/status
register
RTCSR R/W H'0000
H'FFFFFF6E 16
Refresh timer counter
RTCNT R/W H'0000
H'FFFFFF70 16
Refresh time constant register RTCOR R/W H'0000
H'FFFFFF72 16
Refresh count register
RFCR R/W H'0000
H'FFFFFF74 16
Synchronous DRAM For
SDMR W
—
mode register
area 2
H'FFFFD000– 8
H'FFFFDFFF
For
area 3
H'FFFFE000–
H'FFFFEFFF
Notes: For details, see section 12.2.7, Synchronous DRAM Mode Register (SDMR).
* Initialized by power-on resets.
12.1.5 Area Overview
Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32-
bit address spaces. The logical space is divided into five areas by the value of the upper bits of the
address. The physical space is divided into eight areas.
Logical space can be allocated at physical spaces using a memory management unit (MMU). For
details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for
physical spaces.
As listed in table 12.3, this LSI can be connected directly to six areas of memory/PC card
interface, and it outputs chip select signals (CS0, CS2 to CS6, CE2A, CE2B) for each of them.
CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA
interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the
corresponding bytes accessed.
Rev. 5.00 Dec 12, 2005 page 288 of 1034
REJ09B0254-0500