SH7727 Datasheet, PDF (412/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Single Write: The basic timing chart for write access is shown in figure 12.17. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write
data is output at the same time as the write command. In case of the write with auto-precharge
command, precharging of the relevant bank is performed in the synchronous DRAM after
completion of the write command, and therefore no command can be issued for the same bank
until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in
a read access, cycle Trwl is also added as a wait interval until precharging is started following the
write command. Issuance of a new command for the same bank is postponed during this interval.
The number of Trwl cycles can be specified by the TRWL bit in MCR.
Rev. 5.00 Dec 12, 2005 page 340 of 1034
REJ09B0254-0500