SH7727 Datasheet, PDF (1098/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Appendix B Control Registers
Control Register
Module^*1 Bus^*2
Address^*4
Size (Bits)
Access Size (Bits)^*3
LDSARL
LCDC
P2
H'04000C0C 32
32
LDLAOR
LCDC
P2
H'04000C10
16
16
LDPALCR
LCDC
P2
H'04000C12
16
16
LDHCNR
LCDC
P2
H'04000C14
16
16
LDHSYNR
LCDC
P2
H'04000C16
16
16
LDVDLNR
LCDC
P2
H'04000C18
16
16
LDVTLNR
LCDC
P2
H'04000C1A
16
16
LDVSYNR
LCDC
P2
H'04000C1C 16
16
LDACLNR
LCDC
P2
H'04000C1E
16
16
LDINTR
LCDC
P2
H'04000C20
16
16
LDMPPR
LCDC
P2
H'04000C24
16
16
LDPSPR
LCDC
P2
H'04000C26
16
16
LDCNTR
LCDC
P2
H'04000C28
16
16
Notes: 1. Modules
CCN: Cache controller
UBC: User break controller
CPG: Clock pulse generator
BSC: Bus state controller
RTC: Realtime clock
INTC: Interrupt controller
TMU: Timer unit
SCI: Serial communication interface
DMAC: Direct memory access controller
CMT: Compare-match timer
A/D: A/D converter
D/A: D/A converter
SIOF: Serial I/O
PORT: Port control
SCIF: Serial communication interface with FIFO
PCC: PC card controller
AFE: Analog front end interface
H-UDI: User-debugging interface
PPCNT: Peripheral bus interface controller
USBF: USB function controller
USBH: USB host controller
LCDC: LCD controller
2. Internal buses:
L: CPU, CCN, cache, TLB, and DSP connected
I: BSC, cache, DMAC, INTC, CPG, and UDI connected
I2: INTC, CPG, and H-UDI connected
P: Peripheral modules (RTC, TMU, SCI) connected
P1: Peripheral modules (DMAC, CMT, A/D, D/A, PORT, SCIF) connected
P2: Peripheral modules (SIOF, PCC, AFE, PPCNT, USBF, USBH, LCDC) connected
3. The access size shown is for control register access (read/write). An incorrect result
will be obtained if a different size from that shown is used for access.
4. To exclude area 1 control registers from address translation by the MMU, set the first 3
bits of the logical address to 101, to locate the registers in the P2 space.
Rev. 5.00 Dec 12, 2005 page 1026 of 1034
REJ09B0254-0500