SH7727 Datasheet, PDF (302/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
Break Condition Specified to a CPU Data Access Cycle
1. Register specifications
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
• Channel A
Address: H'00123456, Address mask: H'00000000, ASID: H'80
Bus cycle: CPU/data access/read (operand size is not included in the condition)
• Channel B
Address: H'000ABCDE, Address mask: H'000000FF, ASID: H'70
Data:
H'0000A512, Data mask: H'00000000
Bus cycle: CPU/data access/write/word
On channel A, a user break occurs with ASID = H'80 during longword read to address
H'00123454, word read to address H'00123456, or byte read to address H'00123456. On
channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses
H'000ABC00 to H'000ABCFE.
2. Register specifications
BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000,
BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000,
BRCR = H'00300080
Specified conditions: Channel A/channel B independent mode
• Channel A
Address: H'01000000, Address mask: H'00000000
Bus cycle: CPU/data access/read/word
No ASID check is included
• Channel B
Y Address: H'0001F000, Address mask: H'FFFF0000
Data:
H'00004567, Data mask: H'00000000
Bus cycle: CPU/data access/write/word
No ASID check is included
On channel A, a user break occurs during word read to address H'01000000 on the memory
space. On channel B, a user break occurs when word H'4567 is written in address H'0001F000
Rev. 5.00 Dec 12, 2005 page 230 of 1034
REJ09B0254-0500