SH7727 Datasheet, PDF (700/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.2.12 Transmit Control Data Register (SITCR)
This register sets the transmit control data for SIOF. Setting to this register is effective when 1***
is set to FL bit of SIMDR register. This register is initialized at power on reset, software reset, or
transmit reset.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 31 to 16—Transmit Control Data for Channel 0 (SITC015 to SITC00): These bits stores
data to be transfer as transmit control channel 0 data from TXD_SIO. The position of control data
for channel 0 is determined by the setting of CD0A bit of SICDAR register.
This bit is effective when 1 is set to CD0E bit of SICDAR register.
Bits 15 to 0—SIOF Transmit Control Data for Channel 1 (SITC115 to SITC10): These bits
stores data to be transfer as transmit control channel 1 command from TXD_SIO. The position of
control data for channel 1 is determined by the setting of CD1A bit of SICDAR register.
This bit is effective when 1 is set to CD1E bit of SICDAR register.
Rev. 5.00 Dec 12, 2005 page 628 of 1034
REJ09B0254-0500